The present invention relates to semiconductor chip packages, and in particular to a cavity semiconductor package with exposed leads and an exposed die pad, and a method for making the same.
Semiconductor chip packages that have leads and a die pad exposed on the bottom surface are known. Some of the challenges of forming such packages, while ensuring that the leads and die pad remain locked to the package mold, are addressed in co-pending U.S. patent application, Ser. No. 09/395,875, entitled xe2x80x9cPlastic Integrated Circuit Device Package and Micro-Leadframe and Method for Making the Package,xe2x80x9d and in co-pending U.S. patent application, Ser. No. 09/393,016, entitled xe2x80x9cPlastic Integrated Circuit Package and Method and Leadframe for Making the Package,xe2x80x9d both of which are incorporated by reference herein in their entirety.
In these known semiconductor packages, the method of making the package includes molding an encapsulant around the semiconductor die, the die pad and the leads. While this method is suitable for some applications, in other applications such as packaging for power MOSFETs and GaAs chips, it is desirable to maintain a separation between, on the one hand, the package mold material, and on the other hand, the semiconductor die and bond wires. Forming such package with leads exposed on the bottom surface thereof presents special challenges, particularly in ensuring that the leads and die pad remain within the package mold.
Therefore, a need has arisen for a semiconductor chip package and packaging method that meets these challenges. In particular, a need has arisen for a cavity semiconductor package with exposed leads and die pad, where the lead and die pad remain locked to the package mold, and a method for making the same.
Accordingly, a method for assembling a semiconductor chip package is disclosed. In one embodiment, the method includes forming a lead frame with a die pad and leads. At least one of the leads has a tab projecting upward and laterally from a body of the lead. In one embodiment, curved tips are formed on the inner ends of the leads. At least a portion of the lead frame is encapsulated with a mold material to form a package mold having a cavity. The cavity has a floor with a thickness substantially similar to the thickness of the leads so as to expose upper surfaces of the inner ends of the leads. The leads have lower surfaces exposed at the lower surface of the package mold. In one embodiment, the lead tab is entirely encapsulated within the package mold. A semiconductor die is mounted on the lead frame subsequent to the encapsulation of at least a portion of the lead frame. The semiconductor die is enclosed in the package mold by placing a covering such as a lid over the semiconductor die.
In another aspect of the present invention, a semiconductor chip package is disclosed. In one embodiment, the semiconductor chip package includes a semiconductor die mounted on a die pad and a plurality of leads projecting inward toward the semiconductor die. At least one of the leads has a tab projecting upward and laterally from the body of the lead. The package also includes a package mold with a cavity that has a floor. The thickness of the floor is substantially similar to the thickness of the leads, so as to expose upper surfaces of the inner ends of the leads. The leads have lower surfaces exposed at the lower surface of the package mold. The lead tab is entirely encapsulated within the package mold. The package also includes a lid attached to the package mold covering the cavity.
An advantage of the present invention is that the above described packaging method yields a cavity semiconductor package which may be used in applications where contact between the package mold and the semiconductor die and/or bond wires is undesirable. Another advantage of the present invention is that the package and method allow the leads and die pad to be securely held in place by the package mold.